The reduction of the size and reduction of the cost of semiconductor packages is a long-standing desire in the development of semiconductor packages. It is desired to decrease both the footprint of the package, (i.e., the lateral dimensions of the package) so that the space required to mount the package on the board is reduced, and the thickness of the package.
The cost of the semiconductor package can be reduced by reducing the materials costs by, for example, reducing the size of the package or through the choice of the materials. However, a greater cost saving can usually be achieved by simplifying and streamlining the production and assembly processes.
One known approach to solving these problems is to provide a leadless semiconductor package. In this method, a package substrate is prepared by depositing raised metal bumps or regions onto a base or carrier substrate. The raised regions from the substrate which is included in the semiconductor package. The carrier or base substrate is typically a metal foil and is removed after the assembly of the components.
A plurality of package positions can be provided on the base substrate. The arrangement of the raised regions of each package position corresponds to the desired arrangement of the substrate of the package. In leadless packages the raised regions also provide the external contact areas of the package. A chip or contact is mounted onto each bump or raised region using a pick-and-place method. After the bonding and encapsulation processes, the base substrate is removed.
This method has disadvantages as it is costly and time consuming. First, a base substrate including the required raised regions or bumps is prepared and then, the semiconductor chip and contacts are placed one-by-one or serially onto the raised regions. The speed with which this process can be carried out and the packing density of the package positions on the base substrate is limited. This increases the costs of the process and, therefore, the cost of the packages.